Work with architecture team and production engineers to understand the product specification, DFT requirements, clock structure, power management, interconnect and AMD chiplet based infrastructure Define and drive DFT architecture and implementation plan for the project based on these knowledges Work with DFT execution team for Implementation and verification of DFT featu

Provide successful Cache Architecture development and execution using RTL Design, Verilog HDL, and scripting. Collaborate with Cache and CPU Architects to design, document, and execute optimized high performance Cache and Routing Fabric designs. Collaborate with Physical Design to develop RTL that is optimized for physical construction and timing closure. Collaborate with

Plan and drive large, customer facing programs to deploy servers with AMD GPUs with mega data centers, OEMs, and ODMs. Build and lead program core teams. Report execution status to executives, customers, and co workers. Make critical customer communications. Facilitate closure of complex issues requiring multi party alignment of AMD teams, customers, and partners. Manage

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD

Work with internal and external stakeholders to write case studies that are impactful to the AMD business and influential to potential customers Support writing social and web copy for various outbound campaigns including, but not limited to, product campaigns, awareness campaigns, and events Partner closely with the team to help support and assist outbound content develo

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD

Manage technical interaction with OEM/ODM Partners to enable deployment of AMD Instinct Accelerators in Partner systems. Support Partners in the bring up and validation of AMD Instinct GPUs in their system, guide partners on use of AMD tools, qualification test methods, and analysis of test results. Lead the debug of Partner/Customer issues (HW, firmware, driver), working

Work with circuit architects for the implementation of various PHY AMS macros, blocks, and components. Own small to medium size complexity AMS macro designs. Work with IP leads/managers following management priorities, design direction and guidelines, deliver quality macro design meeting specs within schedule Work with layout and physical design activities to meet IP PPA

Define and execute test cases for GPU Virtualization Create and maintain automation test framework for KVM/HYPER V/VMWare hypervisor Analyze and narrow down issues found during test Conduct sanity test, integration test, solution test, Performance test, stress test Reproduce and analyze issues reported by customers PREFERRED EXPERIENCE Knowledge of Windows and Linux envir

Work with architects to understand the product specification, clock structure, power management, interconnect and AMD chiplet based infrastructure Interface with the architecture team, power team, IP design team, SoC integration team, Design Verification and Physical design team to identify complex technical issues/risks and optimize the implementation efficiency and cost

Provide comprehensive onsite administrative support for the Data Center GPU & Accelerated Processing team in Santa Clara, accommodating onsite, hybrid, and traveling employees. Interface with executive management, customers, and visitors, redirecting inquiries and issues as needed. Manage departmental financial processes, including budgets, contracts, purchase orders, pay

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build t

Execute on RTL design and coding for various sections of the processor core pipeline and related logic Collaborate with a team of hardware and software engineers to define the high level architecture Participate in the definition of microarchitecture of next generation high performance processor cores Contribute to design verification, synthesis, power reduction, timing c

Working with a multi discipline and international team of engineers on design for debug (DFD) architecture, design and methodology initiatives. Performing DFD IP RTL design per micro architectural specifications. Performing DFD RTL integration, synthesis, equivalency checking, timing analysis and closure including defining design constraints. Writing and maintain DFD docu

Develop and run financial models to enable quick scenario planning. Bridge between the business unit and supporting finance teams. Monitor yields, cost, pricing, and product gross margins to ensure business is tracking to deliver gross margin and contribution operating profit goals. Creates Monthly Operations Forecast (MOF) for business unit. Coordinate across accounts, F